In recent years, vertical transistors have been proposed as a technology for miniaturizing transistors. A vertical transistor is a transistor which employs as a channel a semiconductor pillar (base pillar) extending in a direction (Z-direction) perpendicular to the main surface of a semiconductor substrate (the surface on which the transistor is formed, in other words the XY plane defined by the X-direction and the Y-direction).
More specifically, in a vertical transistor a semiconductor pillar is provided rising from the semiconductor substrate, and a gate electrode is provided at the periphery of the semiconductor pillar, with the interposition of a gate insulating film. A drain region and a drain electrode are provided at the bottom of the semiconductor pillar, and a source region and a source electrode are provided at the top of the semiconductor pillar.
The planar surface area occupied by the vertical transistor is smaller than in a conventional transistor in which the channel is disposed parallel to the main surface of the substrate, and the planar surface area occupied by the transistor does not increase even if the channel length (gate length) is increased. Short channel effects can therefore be suppressed even without increasing the planar surface area occupied by the transistor. Further, the vertical transistor has the advantage that the channel can be fully depleted, and it is therefore possible to obtain a satisfactory S-value (Subthreshold swing value) and a large drain current.
Here, in order to obtain a high current-driving capability while maintaining the transistor characteristics, in some cases a semiconductor device employing a vertical transistor is provided with a plurality of semiconductor pillars, and upper diffusion layers and lower diffusion layers provided at the tops and bottoms of the plurality of semiconductor pillars are respectively connected in parallel. In this case, to achieve the parallel connections between the upper diffusion layers, contact plugs having a fatness (the size of a cross section cut through a plane parallel to the substrate surface of the silicon substrate) that is less than that of the semiconductor pillars are connected individually to the upper diffusion layer of each vertical transistor, and the upper surfaces of the contact plugs are connected to one another using a single wiring line.
Patent literature article 1 discloses a configuration of one parallel transistor in which four vertical transistors are connected in parallel.